The invention relates to an integrated multiplier circuit defined in the preamble of independent claim 1.
It is known from the prior art a so-called Gilbert cell which is widely used in integrated multiplier circuits in communications systems, especially in mobile stations. Multiplier circuits are used in integrated IF parts, such as mixers and variable amplifiers. The Gilbert cell is based on current control.
Another prior-art multiplier is disclosed in: Song, H.-J. and Kim C.-K. 1990 An MOS Four-Quadrant Analog Multiplier Using Simple Two-Input Squaring Circuits with Source Follower, IEEE Journal of Solid-state Circuits 25, 3, pp. 841-847. This squaring multiplier is based on a mathematical equation in which the difference of the squares of the sum and difference of two signals gives the product of the signals:
(x+y)2xe2x88x92(xxe2x88x92y)2=4xyxe2x80x83xe2x80x83(1),
where x is a first signal and y is a second signal.
The squaring is realized using e.g. an MOS (Metal Oxide Semiconductor) transistor in which the channel current is squarely proportional to the gate voltage. However, the multiplier is preferably realized using bipolar transistors because of their higher speed. The collector current iC of a bipolar transistor is:                                           i            C                    =                                    I              S                        ⁢                          e                                                v                  BE                                                  V                  T                                                                    ,                            (        2        )            
where the parameters of the bipolar transistor are: saturation current IS, base-emitter voltage VBE and thermal voltage VT. The exponent function is approximated with the first four terms of an infinite Taylor series:                                           i            C                    =                                                    I                S                            ⁢                              exp                ⁡                                  (                  x                  )                                                      ≈                                          I                S                            ⁢                              {                                  1                  +                                                            1                                              1                        !                                                              ⁢                    x                                    +                                                            1                                              2                        !                                                              ⁢                                          x                      2                                                        +                                                            1                                              3                        !                                                              ⁢                                          x                      3                                                                      }                                                    ,                            (        3        )            
where                               x          =                                    v              BE                                      V              T                                      ,                            (        4        )            
wherein the parameters shown are the base-emitter voltage VBE and thermal voltage VT of the bipolar transistor.
Mixers are usually based on a double-balanced structure in which the outputs of four differently phased mixers are summed in order to cancel harmonic effects. Mathematically, the balancing can be expressed as
(x+y)2+(xe2x88x92xxe2x88x92y)2xe2x88x92(xxe2x88x92y)2xe2x88x92(xe2x88x92x+y)2=8xyxe2x80x83xe2x80x83(5)
After substituting the first four terms of the Taylor series into the equation we are still left with the product of input signals:                                                         e                              x                +                y                                      +                          e                                                -                  x                                -                y                                      -                          e                              x                -                y                                      -                          e                                                -                  x                                +                y                                              =                                    8                              2                !                                      ⁢            xy                          ,                            (        6        )            
after changing the x and y into symbols representing output signals the final mathematical equation can be given as                                           e                                          V                BE                            +              x              +              y                                +                      e                                          V                BE                            -              x              -              y                                -                      e                                          V                BE                            +              x              -              y                                -                      e                                          V                BE                            -              x              +              y                                      =                              8                          2              !                                ⁢          xy                                    (        7        )            
A problem with the known multiplier circuit based on a Gilbert cell is that it requires a relatively high operating voltage. Normally, it is not possible to decrease the operating voltages of integrated analog circuits only by using new technologies and by modifying design rules. Currently, the operating voltages of analog high-frequency circuits are about 5 V. The operating voltages of many digital circuits are 3.3 V. As the digital components of mobile stations do not need high operating voltages but the analog parts do, the main thing to do in order to save power is to decrease the operating voltages of analog circuits. As a result of the decrease in the operating voltage, many of the circuit connections used in analog high-frequency circuits become useless because then the junction voltages of many transistors cannot be connected in series. Therefore, partly new circuit connections are needed.
A further problem with low operating voltages is the characteristic of integration that causes great parameter variation in the circuits realized. Real resistor values vary by about xc2x120% and uncompensated bias current by about xc2x125%. The effect of parameter variation has to be taken into account in the circuit design. When specifying the operating point, safety margins are used. With about one kilo-ohm resistor and several milliamps of current which are typical of IF parts in a mobile station, the voltage between the terminals of the resistor varies from 0.6 V to 1.5 V at the most. This variation causes special problems because of the low operating voltage since the safety margins are narrow.
A further disadvantage of the known multiplier circuits based on Gilbert cells is that their connection together as low-voltage structures is problematic. DC level transfer between blocks has usually been realized by means of emitter followers which have a voltage shift of xe2x88x920.8 V. This is a lot when compared to a 3-volt operating voltage. Isolating the DC voltages of the blocks by means of capacitors at the intermediate frequency is possible but impractical as at the frequencies used the size of the capacitors will be be fairly big and, on the other hand, the generation of bias voltages and currents for the next stage becomes more difficult.
An object of the invention is to provide a new integrated exponential cell with which the disadvantages described above can be eliminated. An object of the invention in particular is to provide a new exponential cell which operates at a low operating voltage.
The integrated multiplier circuit according to the invention is characterized in what is expressed in the characterizing part of independent claim 1. Preferred embodiments of the invention are disclosed in the characterizing parts of the dependent claims.
The integrated multiplier circuit according to the invention comprises four differently phased exponential cells the outputs of which are summed. In accordance with the invention, each exponential cell is realized using bipolar transistors such that the interdependence of input signals and output signals is exponential, and each exponential cell includes a constant current source to set the operating point of the bipolar transistors, said constant current source preferably being based on an MOS transistor.
In an embodiment of the multiplier circuit each exponential cell has differential inputs which in the different exponential cells are connected crosswise, the first of said inputs being connected to the base of a squaring bipolar transistor and the second to the emitter of a squaring bipolar transistor through a voltage follower, and in which the current through the squaring bipolar transistors of two exponential cells is directed through the same load resistor so that differential output signals are taken from the collectors of the squaring bipolar transistors.
In an embodiment of the multiplier circuit the voltage follower is realized with an emitter follower implemented using a bipolar transistor such that the bias current of the emitter follower is set clearly higher, preferably ten times higher, than the bias current of the squaring bipolar transistor.
In an embodiment of the multiplier circuit the squaring bipolar transistor includes an emitter resistor.
In an embodiment of the multiplier circuit the multiplier circuit is realized using the BiCMOS technology.
An advantage of the invention is that the multiplier circuit and especially its exponential cell are suitable for low operating voltages. The exponential cell has only one transistor stage, compared to the two transistor stages connected in series in the Gilbert cell. The theoretical minimum operating voltage of the Gilbert cell is about 3 V, whereas with the exponential cell according to the invention the operating voltage can be easily realized at the 3-volt level. Furthermore, it is worth noting that the theoretical minimum operating voltage of the exponential cell is clearly lower than this.
Another advantage of the invention is that the multiplier circuit and especially its exponential cell are suitable for a wide frequency range extending from DC to hundreds MHz. The upper frequency limit depends on the technology.
A further advantage of the invention is that the multiplier circuit and especially its exponential cell are suitable for the BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) technology, i.e. a semiconductor technology which comprises both bipolar transistors and MOS transistors, and for bipolar technologies. This semiconductor technology especially facilitates said low operating voltage (down to 2.5 V and below) and high upper frequency limit.
A still further advantage of the invention is the simple exponential cell structure realized using bipolar transistors. The feedback and nonlinearity problems associated with the bipolar structure have been solved in a satisfactory manner. The exponential cell according to the invention operates only at a certain operating point correctly dimensioned and at relatively low signal levels.